FIG. 1 shows circuitry for controlling a flash memory cell. Memory cell 2 comprises a single transistor 4, having a control gate CG and a floating gate FG, a source S and a drain D. The source S may be connected either to a ground voltage VGND, or to a programming voltage VPP, by source voltage switch 8, according to a signal applied to an erase control input 10. The drain D of transistor 4 is connected to a bitline 12, which may be connected either to a sense amplifier circuit 16 or to a programmable load circuit 18 by a bitline switch 14, according to a select input 20. The programmable load circuit 18 is controlled by load control signals 22. The sense amplifier circuit 16 provides an output to a data line 24. The control gate of transistor 4 is connected through word line 26 to a gate voltage switch 28. This permits the control gate CG to be connected to the ground voltage VGND, the programming voltage VPP or a supply voltage Vcc, according to control signals applied to program and erase control inputs 30, 10 respectively. Vcc is 5V for a memory device operating with a 5V supply, and about 5V for a memory device operating with a 3V supply. VPP may be approximately 12V.
The flash memory cell 2 has three modes of operation.
In program mode, a 0 is written to the cell. The control gate CG is connected to the program voltage VPP. The source S is connected to the ground voltage VGND and drain D is connected to the programmable load circuit 18, programmed to place the drain at about 5V. Thus, the floating gate FG is negatively charged, making the transistor less conductive for a given control gate voltage.
In erase mode, a 1 is written into the cell. The control gate CG is connected to ground voltage VGND, the source S is connected to program voltage VPP. The bitline switch 14 is set to allow bitline 12 to float at around 1V. The charge on FG is reduced, making the cell more conductive. After a sufficient time, a 1 is considered written into the cell.
In read mode, voltages are applied to transistor 4 such that a relatively low current will flow when a 0 has been written into the cell, and a relatively high current will flow when a 1 has been written into the cell. The contents of each memory cell may thus be determined. The control gate CG and the wordline 26 are connected to the supply voltage Vcc. The source is connected to ground VGND. Bitline 12 is connected to the sense amplifier circuit 16, which provides a bias of around 1V. The amount of current flowing through the transistor 4 depends on its programmed or erased state. The sense amplifier 16 detects the level of the current and places the dataline 24 in a logic state indicative of the state of the cell 2.
In a flash memory device, many cells such as that shown in FIG. 1 are connected and provided with addressing circuitry. Each cell, however, functions as described above, in its three possible states. Commands are provided to the memory device to control its functionality. The circuitry required to enact the control functions is included in the same integrated circuit as the memory cells.
Command words are loaded by use of input/output (I/O) terminals of the flash memory device, loading of command words being controlled by a clock signal applied to a write enable or chip enable terminal. The command present on the I/O terminals must be latched internally on the next rising edge of an applied clock signal. The command may require latching of other data present on device terminals, and thus must be interpreted and acted upon before the following falling edge of the input clock.
The use of relatively high voltages and fast digital switching speeds means that a flash memory circuit is a very noisy environment.
Flash memory devices interpret and validate the command words using logic circuitry known as a command user interface, advantageously realized by use of a state machine. In this context, a state machine is a logic circuit with a finite number of possible states, having a number of inputs and outputs; some of the inputs being connected to some or all of the outputs. In such a circuit, a current state is defined by current values of the inputs connected to outputs of the state machine. A clock signal is usually applied and the state machine changes state at each clock cycle, according to signals applied to the inputs.
The logic circuitry required within a state machine may be implemented in a number of ways. Preferably, a programmable logic array (PLA) implementation is used. PLAs have the advantages that they are usually of a compact structure; their generation and circuit layout may easily be automated by use of a suitably programmed computer; the operation of an integrated circuit PLA may be modified, or `programmed`, at the fabrication stage of the integrated circuits by changes in one or two masks.
A PLA is generally composed of two logic planes, an input plane and an output plane. Each plane receives inputs which are applied to gate terminals of transistors within the logic plane, and provides outputs to output nodes. The inputs to the input plane are the inputs to the PLA. The outputs of the input plane are intermediate nodes. The inputs to the output plane are connected to the intermediate nodes. The outputs of the output plane are the outputs of the PLA.
The input plane may provide an AND function, and the output plane may provide an OR function. Alternatively, both planes may provide a NOR function. These functions are defined by the type and connectivity of the transistors used and the signals applied to their gates.
The NOR-NOR configuration described has particular advantages in that it is the simplest to implement in CMOS logic. NOR stages have a number of transistors equal to the number of inputs connected in parallel. Addition of further parallel transistors for accommodating further inputs does not affect the operating speed of the stage.
FIG. 2 shows a circuit diagram of a PLA using static pull-ups both on its input plane 40 and its output plane 42. Both the input plane and the output plane have a NOR logic function. Input signals INA, INB, INC are applied to the gates of N-channel transistors 50, 52; 54, 56; 58, respectively. Each of the transistors has its source grounded and its drain connected to a first terminal of an intermediate node pull-up resistor 59, 60, 62, through intermediate nodes 66, 68, 70, respectively. Each of the intermediate node pull-up resistors has a second terminal connected to a supply line 73.
Each of the intermediate nodes is connected to gate terminals of one or more N-channel transistors 66a, 66b, 68b, 70a. Each of these transistors has its source grounded and its drain connected to an output node 74a, 74b, each of which is respectively connected to a first terminal of a pull-up resistor 76, 80. The pull-up resistors each have a second terminal connected to the voltage supply line 73. The output nodes 74a, 74b supply outputs of the PLA OUTA, OUTB.
The intermediate nodes 66, 68, 70 approach the voltage Vcc of the supply line 73 due to conduction by the intermediate node pull up resistors unless an associated N-channel transistor 50, 52, 54, 56, 58 is conductive due to a high input signal being applied to its gate. The intermediate nodes thus perform NOR functions by comparison with associated input signals.
Similarly, the output nodes provide a NOR function with respect to the associated intermediate node signals. Indicating the intermediate node signals by the node labels,
66=not(INA+INB); PA1 68=not(INB+rNC); PA1 70=notINA. PA1 0UTA=not(66+70); PA1 0UTB=not(66+68); PA1 OUTA=INA.INB+INA.INC; PA1 OUTB=INA.INB+INA.INC+INB.INC.
At the output nodes,
giving:
There are several DC current paths from Vcc to GND, which are continually conductive, and lead to a large current consumption for the circuit taken as a whole.
An alternative method for the implementation of PLAs avoids the large current consumption by static pull-ups. `Dynamic` pull-ups are used, which perform a pull-up function and hence enable a DC conduction path only when commanded by a pull-up signal.
FIG. 3 shows a modification of the PLA of FIG. 2 wherein the static pull-ups are replaced by dynamic pull-ups. The resistors 59, 60, 62 and 76, 80 are respectively replaced by transistors 92, 94, 96, controlled by a pull-up signal IPU, and transistors 100, 104, controlled by a pull-up signal OPU.
Some time is needed for charging the output nodes to the high voltage Vcc, to be able to provide high outputs OUTA, OUTB. To improve operating speed, the pull-up transistors and pull-up signal OPU are used to charge the output nodes, just before the intermediate node pull-up transistors are rendered conductive, to improve the operating speed of the PLA.
In an initial condition of the PLA, all input signals INA, INB, INC are held in a high state. All input plane transistors are conductive, and the intermediate nodes are held at the ground voltage. All output plane transistors are therefore off. Output node pull-up signal OPU holds pull-up transistors 100, 104 in a conductive state, and the output nodes are thus charged to Vcc. The output nodes 74a, 74b remain charged to the voltage of supply line 73, as none of the associated N-channel transistors 66a, 70a; 66b, 68b is in a conductive state.
As soon as an input is ready for evaluation, a low signal may be applied to some of the inputs of the PLA, rendering some of the input plane transistors non-conductive. The output node pull-up signal OPU becomes inactive. The intermediate nodes 66, 68, 70, approach the voltage Vcc of the supply line 73 unless an associated N-channel transistor 50, 52, 54, 56, 58 is still held in a conductive state due to a high input signal being applied to its gate.
Any high intermediate node signal applied to gates of output plane transistors will cause the associated output node 74a, 74b to become discharged. The charged or uncharged state of the output nodes is reflected by high or low voltages at outputs OUTA, OUTB.
Inputs to the PLA are usually arranged so that both the positive and inverted values of an input signal INA, notINA are applied, to separate inputs of the PLA.
Output signals are usually buffered and stored in temporary storage devices, such as master/slave D-type latches, driven by two phase clock signals such that when the latch is clocked, the outputs of the PLA are stored before the new feedback value is output and is passed back to the inputs of the PLA.
FIG. 4 illustrates an output latch of known type. An output signal OUTA is connected to drain terminal of P-channel transistor 112 and an input of an inverter 114. The source terminal of transistor 112 is connected to supply voltage Vcc. An output of inverter 114 is connected both to a gate terminal of transistor 112 and to an input of pass gate 116. Gate terminals of passgate 116 are connected to clock signal CLK1 and its inverse, notCLK1. An output of pass gate 116 is connected to an input of a latch 122 which comprises two inverters connected in inverse parallel, and further connected to reset circuitry 126. An output of latch 122 is connected both to an input of inverter 132 and an input of pass gate 134. The output of pass gate 134 provides an output signal notLOUT. The output of inverter 132 provides another output signal, LOUT. The gate terminals of passgate 134 are connected to clock signals CLK2 and notCLK2. The reset circuitry 126 is connected to receive a reset signal RST and a reset polarity input notR1, and receives supply Vcc and ground GND voltages.
This output latch works as follows. The latch 122 holds a value at its output, and the inverse of this value at the input. The output of the latch may be reset to 1 by applying RST=1 and notR1=1. It may be reset to 0 by applying RST=1 and notR1=0.
Once the output nodes have been precharged by the output node pull-up transistors 100, 104 controlled by signal OPU, the output of the inverter 114 is 0. Transistor 112 is a resistive channel device, and acts as a keeper. It is rendered sufficiently conductive by the low output of inverter 114 to hold the output node charged and to compensate for any current leakage paths which would tend to discharge the output node. The output node thus retains its precharged state, even after the output node pull-up transistors of the PLA have been turned off. This avoids the need to leave the output node in a floating state, since the high noise levels present in a flash memory device could easily prompt the discharge of such floating nodes.
If the output node OUTA is pulled low during the evaluation of the PLA, a high voltage is applied to the gate of transistor 112, and node OUTA is pulled fully to ground, with no steady state DC current. The output of the inverter 114 is passed by passgate 116 to the input of latch 122, when the clock signal CLK1 is high. The output of latch 122 is inverted by, and is available at the output (LOUT) of, inverter 132. The output of latch 122 is passed to the output notLOUT by passgate 134 when CLK2=1. The output node OUTA is again precharged during the next active (low) period of signal OPU. The output of inverter 114 thus returns to a low value and keeper 112 is re-activated.
To propagate a signal from the output node OUTA to the output notLOUT of the latch requires a high level firstly on CLK1 then CLK2. The two clocks should not overlap, otherwise any spurious signals on OUTA would be transmitted to notLOUT. The output latch thus transmits the inverse of OUTA to LOUT two inverter delays after a rising edge of CLK1, and to notLOUT after rising edges on both CLK1 and CLK2 (in that order).
Preferably, the input signals to the PLA are applied by an input latch and driver circuit. Such a circuit functions to apply a low signal to either a positive or inverted signal input INA, notINA, as appropriate to the polarity of the input signal IN, at a falling edge of a clock signal MASCLK.
FIG. 5 shows a known implementation of an input driver. It comprises an input latch 139 and an input driver 140. An input signal IN is applied to an input of an inverter 141. The output of inverter 141 is connected to an input terminal of pass gate 142. The output of pass gate 142 provides a signal to an input of latch 148, and to a drain terminal of P-channel transistor 150. The latch 148 is composed of two inverse parallel connected inverters. The source of transistor 150 is connected to the supply voltage Vcc 73. The gate terminal of transistor 150 is connected to an active-low reset to zero signal notR0. The output of latch 148 is connected to an input of inverter 151, whose output provides the input latch signal notN.sub.-- EN. This is the latched value of IN, as at the previous falling edge of MASCLK.
Within the input driver 140, two passgates 152, 154 receive notN.sub.-- EN on the gates of the N-channel transistor and the P-channel transistor respectively. The signal notN.sub.-- EN is inverted to N.sub.-- EN by inverter 156 to supply the gates of the P-channel transistor of passgate 152 and the N-channel transistor of passgate 154. The intermediate node pull-up signal IPU is applied to the inputs of passgates 152, 154. The outputs of these passgates are signals INA, notINA respectively. These two output signals are each connected to a drain terminal of a P-channel transistor 160, 162 respectively. The source terminals of these P-channel transistors are connected to supply voltage Vcc 73, and gate terminals are connected to notN.sub.-- EN and N.sub.-- EN respectively.
The input driver of FIG. 5 functions as follows. Depending on the value of notN.sub.-- EN, either passgate 152 or passgate 154 is conducting. For the non-conductive passgate, the associated P-channel transistor 160, 162 is conductive. One of the two outputs INA, notINA will thus have the value of the applied IPU signal; the other will be held high by transistor 160 or 162. While the IPU signal is inactive (high), both INA and notINA are high. When IPU becomes active (low), one of the outputs INA, notINA will become low also, for the duration of the low level of IPU. The reset to zero signal R0 is used to initially place the latch in its zero output state, hence setting notN.sub.-- EN high, and rendering passgate 152 conducting.
The signal IN is buffered and inverted by inverter 141, and transmitted by passgate 142 when MASCLK is high. Provided that signal notR0 is inactive, latch 148 stores the value of IN at its output. The output of latch 148 is inverted by inverter 151 to become signal notN.sub.-- EN, the output of the input latch.
The inputs to the PLA are all held high at all times other than during the evaluation of the input plane. This ensures that all input plane transistors are conductive, the intermediate nodes are held at the ground voltage, the output plane transistors are non-conductive, and the output nodes retain their charged state. The evaluation of the input plane takes place while the intermediate node pull-up signal is active (low). Thus, by defining one of INA, notINA as being high, and the other as being equal to IPU, a low input signal is only applied to the PLA during the active phase of IPU. This low is applied to INA if IN=0, and to notINA if IN=1. INA and notINA are only the inverse of each other during the period of evaluation of the input plane.
FIG. 6 shows a block diagram of the prior art PLA circuit as described above. The input latch A2 latches the value of the input signal IN on the falling edge of MASCLK. The output notN.sub.-- EN is this latched input value.
The input driver A4 applies the input signals INA, notINA to the input plane when the IPU signal is active (low), according to the value of notN.sub.-- EN.
The input plane A6 evaluates the input signals INA, notINA while IPU is low, and produces levels at the intermediate node A8, as functions of the input signals.
When OPU becomes active (low), the output plane A10 evaluates the intermediate node levels, and produces levels OUTA which are functions of the intermediate node levels. These levels OUTA are admitted to output latch A12 when clock signal CLK1 is active (high), and transmitted to the PLA output when clock CLK2 is high.
Logic arrangements other than NOR-NOR may be used in the design of PLAs. However, both the AND-OR and the related NAND-NOT-NOR arrangement are more complex, requiring many additional transistors. In particular, the NAND-NOT-NOR arrangement has a NAND stage at its inputs, which is relatively slow, and introduces a significant delay, particularly with a PLA having a large number of inputs. The inverter needed in this arrangement, between the input and output planes, introduces another delay and increases the semiconductor area required to implement such a PLA. The currently described PLA notably does not have any buffers or inverters at the intermediate nodes, this speeding up the operation of the circuit. During the operating cycle of such a PLA, some nodes are charged and left floating. This is particularly undesirable in the application of a flash memory device, as high voltages present on a flash memory chip may cause hot carrier conduction and damage, and may lead to the discharge of the floating node, and hence errors in the PLA output.
Unpublished European patent application No. 94830072.8, which is not admitted to be prior art, to the current application suggests the use of a dummy PLA circuit associated with a PLA circuit, but explicitly excludes NOR-NOR PLA circuits as being not viable. It provides a timing circuit for use with a NAND-NOT-NOR PLA for use in flash memories.
U.S. Pat. No. 4,760,290 describes a programmable logic array with an incorporated delay circuit, allowing timing pulses to be generated. This circuit requires at least two clock edges to evaluate the PLA, which slows operation when compared to a circuit operating on a single clock edge. The delay circuitry is integrated into the PLA arrays, so a separate delay circuit is necessary for each PLA to be controlled. The operation of the circuit according to this U.S. patent relies on the use of floating nodes to store charges representing information. This is not acceptable in high voltage, high noise environments, where noise signals induce discharging of such floating nodes. The circuit described also operates from an external clock, and cannot react quickly to asynchronously applied signals. The following clock transition must be awaited, twice in this circuit, which significantly slows operation of the circuit.
The command user interface in a flash memory device requires that the state machine operates from a single-phase clock. A command is latched on a single rising edge and must be interpreted and acted upon before the next rising edge. The falling edge is used in some commands to latch the input address. The output of the PLA controls whether the address is going to be latched. Therefore this output must be present before the next falling edge if the chip is to know whether or not to latch an address. The minimum time between falling edges of a clock cycle used for flash memory devices is typically between 20 and 40 ns. The outputs of the command user interface must therefore be valid within this time.
As described above, NOR-NOR PLA circuits require that pull-up signals are active at the correct times. The known timing methods require the use of two clock signals IPU, OPU to turn on pull-up transistors only when they are required for the propagation of signals through the PLA, output latches being provided to retain the output level once the pull-up signal becomes inactive. Buffers may also be provided at the intermediate nodes for storage of their values. This method and circuit has the disadvantage that two clock phases IPU, OPU are required to operate the circuit. Each clock is active for a short part of each cycle, and each clock is generated by a monostable, triggered from either the rising or falling edge of a master clock signal. This is not acceptable in applications which require input data to be latched on one edge of a clock signal and the output to be available before the next edge of the clock cycle. In such applications, static pull-up PLAs are used for high speed of operation, but consume a large amount of current.